IEEE 1850-2005 pdf download IEEE Standard for Property Specification Language (PSL)
1.Overview
1.1 Scope
This standard defines the property specification language (PSL), which formally describes electronic systembehavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaceswith various standard electronic system design languages.
1.2 Purpose
The purpose of this standard is to provide a well-defined language for formal specification of electronicsystem behavior, one that is compatible with multiple electronic system design languages, including IEEEStd 1076TM (VHDL), IEEE Std 1364TM (Verilog, IEEE P1800M'(SystemVerilog, and IEEE P1666MSystemC), to facilitate a common specification and verification flow for multi-language and mixedlanguage designs.
1.2.1 Background
The complexity of Very Large Scale Integration (VLSI) has grown to such a degree that traditionalapproaches have begun to reach their limitations, and verification costs have reached 60%-70% ofdevelopment resources. The need for advanced verification methodology, with improved observability ofdesign behavior and improved controllability of the verification process, has become critical. Over the lastdecade, a methodology based on the notion of “properties” has been identified as a powerful verificationparadigm that can assure enhanced productivity, higher design quality and, ultimately, faster time to marketand higher value to engineers and end-users of electronics products. Properties, as used in this context, areconcise, declarative, expressive and unambiguous specifications of desired system behavior, that are used toguide the verification process.IEEE Std 1850 PSL is a standard language for specifying electronic systembehavior using properties. PSL facilitates property-based verification using both simulation and formaverification, thereby enabling a productivity boost in functional verification.
1.22 Motivation
Ensuring that a design’s implementation satisfies its specification is the foundation of hardware verification.Key to the design and verification process is the act of specification. Yet historically, the process ofspecification has consisted of creating a natural language description of a set of design requirements. Thisform of specification is both ambiguous and, in many cases, unverifable due to the lack of a standardmachine-executable representation. Furthermore, ensuring that all functional aspects of the specificationhave been adequately verified (that is, covered) is problematic.
The IEEE PSL was developed to address these shortcomings. It gives the design architect a standard meansof specifying design properties using a concise syntax with clearly-defined formal semantics. Similarly, itenables the RTL implementer to capture design intent in a verifiable form, while enabling the verificationengineer to validate that the implementation satisfies its specification through dynamic (that is, simulation)and stafic (that is, formal) verification means. Furthermore, it provides a means to measure the quality of theverification process through the creation of functional coverage models built on formally specifiedproperties. In addition, it provides a standard means for hardware designers and verification engineers tocreate a rigorous and machine-executable design specification.
1.2.3 Goals
PSL was specifically developed to fulfill the following general hardware functional specificationrequlrements:
Easy to learn, write, and read
Concise syntax
Rigorously well-defined formal semantics
Expressive power, permitting specifications of a large class of real-world design propertiesKnown efficient underlying algorithms in siulation, as well as forimal verification
1.3 Usage
PSL. is a language for the formal specification of hardware. It is used to describe properties that are requiredto hold in the design under verification. PSL provides a means to write specifications that are both easy toread and mathematically precise. lt is intended to be used for functional specification on the one hand and asinput to functional verification tools on the other. Thus, a PSL specification is an executable specification oa hardware design.
1.3.1 Functional specification
PSL can be used to capture requirements regarding the overall behavior of a design, as well as assumptionsabout the environment in which the design is expected to operate. PSL can also capture internal behavioralrequirements and assumptions that arise during the design process. Both enable more effective functionalverification and reuse of the design.
IEEE 1850-2005 pdf download
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