IEEE 1647-2008 pdf download IEEE Standard for the Functional Verification Language e
1.3 Verification environments
Electronic systems are integrated circuits (ICs), boards, or modules combining multiple ICs together, alongwith optional embedded processors and software components. Electronic systems are built to specificationsthat anticipate the environment in which such systems are expected to function and define the expectedsystem functionality. Functional verification measures how well a system meets its specification. Even witmoderately complex systems this question cannot be answered by inspection. For all modern electronicsystems, a sophisticated verification process needs to accompany the design process to ensure compliancewith the specification.
Many electronic design automation (EDA) tools are used to carry out the functional verification processThe most prominent functional verification method, used to verify virtually all system designs, is calleddvmamic verification or simulalion-hased verification. Simulation-based verification mmakes use of afunctional model of the system being designed. The functional model is simulaled in the context of a mock-up of the anticipated system environment. This mock-up is called the verification environmen!.
There are many requirements a verification environment needs to fulfill, as followsIt needs to create input stimulus and feed it into the system being verified.It needs to collect the output from the system being verified, as well as the state of selected internalnodes.
It needs to check that the output matches the expectations, based on the functional requirements, thestate of the system being verified, and the inputs provided.
lt needs to measure functional coverage: the extent to which functions of the system being verifiedhave been exercised by the verification environment,
lt needs to facilitate error dentification, isolation, and debug. For that purpose, test environmentscontain combinational and teporal assertions, as well as various messaging and loggingcapabilities.
The verification environment needs to be able to mimic all possible variations and configurations the
system being verified might face in practiceThe verification environment neds to be able to throw a wide variety of error conditions at thesystem being verified, in order to test error handling and error recovery.The verification environment should be easily controllable, to allow steering by the verificationengineers.
he verificaton environment is a primary component in a simulation-based verification process. Theenvironment needs to drive the system being verified through enough diverse scenarios to cover astatistically meaningful portion of the systems state space. Coverage data collected throughout the processshould provide the foundation to an informed decision about the production readiness of the system beingdesigned.
Sophisticated verificationenvironments are complex software systems, representing a significantinvestment. Reuse of verification components is a primary way of minimizing this investment. Reusability istypically an artifact of a well thought-out software architecture, but in the case of e, the language itselfacilitates reuse through asnect-oriented programming (AOP) constructs and the semantics of generation.
“he e functional verification language can facilitate the creation of sophisticated verification cnvironmentsas e features many constructs that autotmate and support commimonverification enyironment tasks
IEEE 1647-2008 pdf download
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