IEEE 1364-2005 pdf download Sponsored by the Design Automation Standards Committee
1.4 Use of color in this standard
This standard uses a minimal amount of color to enhance readability. The coloring is not essential and doesnot affect the accuracy of this standard when viewed in pure black and white. Color is used to show crossreferences that are hyperlinked to other portions of this standard. These hyperlinked cross references arehown in underlined-blue text (hyperlinking works when this standard is viewed interactively as a PDF file).
1.5 Contents of this standard
A synopsis of the clauses and annexes is presented as a quick reference. There are 28 clauses and 9 annexesAll clauses, as well as Annex A, Annex B, and Annex G, are normative parts of this standard. Annex CAnnex D, Annex H, and Annex I are included for informative purposes only.
EEE Std 1364-2005 has deprecated the task/function (TF) and access (ACC) routines, which were specifiedpreviously in Clause 21 through Clause 25, Annex E, and Annex F of IEEE Std 1364-2001, Clause 20 hasoeen modified to reflect this change. The text of deprecated clauses and annexes has been removed from thisversion of the standard, but the clause headings have been retained. See the corresponding clauses in IEEEStd 1364-2001 for the deprecated text.
Clause 1 discusses the conventions used in this standard and its contents.
Clause 2 lists references to other publications that are required in order to implement this standard.
Clause 3 describes the lexical tokens used in Verilog HDL source text and their conventions, It describeshow to specify and interpret the lexical tokens.
Clause 4 describes net and variable data types. This clause also discusses the parameter data type forconstant values and describes drive and charge strength of the values on nets.
Clause 5 describes the operators and operands that can be used in expressions.
Clause 6 compares the two main types of assignment statements in the Verilog HDL-continuousassignments and procedural assignments. It describes the continuous assignment statement that drives valuesonto nets.
Clause 7 describes the gate- and switch-level primitives and logic strength modeling
Clause 8 describes how a primitive can be defined in the Verilog HDL and how these primitives areincluded in Verilog HDL models.
Clause 9 describes procedural assignments, procedural continuous assignments, and behavioral languagstatements.
Clause 10 describes tasks and functions-procedures that can be called from more than one place in abehavioral model. It describes how tasks can be used like subroutines and how functions can be used todefine new operators. The clause describes how to disable the execution of a task and a named block ofstatements.
Clause 11 describes the scheduling semantics of the Verilog HDL
IEEE 1364-2005 pdf download
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