IEEE 1149.1-2013 pdf download IEEE Standard for Test Access Port and Boundary-Scan Architecture
Once the instruction has been loaded, the selected test circuitry is configured to respond. In some cases, however, itis necessary to load data into the selected test circuitry before a meaningful response can be made. Such data areloaded into the component serially in a manner analogous to the process used previously to load the instruction.Note that the movement of test data has no effect on the instruction present in the test circuitry.
After execution of the test instruction, based where necessary on supplied data, the results of the test can beexamined by shifting data out of the component to or through the bus master.
Note that in cases where the same test operation is to be repeated but with diferent data, new test data can be shiftedinto the component while the test results are shifted out. There is no need for the instruction to be reloaded.
Operation of the test circuitry may proceed by loading and executing several further instructions in a manner similarto that described and would conclude by returning control from the test circuitry to system circuitry. Note that thestate of the syste logic may be indeterminate, and care is required in returning to system operation.
1.2.2 Use of this standard to test an assembled product
This subclause outlines the use of the boundary-scan circuitry defined by this standard during the process of testingan assembled product such as a printed circuit board.
The test problem for any product constructed from a collection of components can be decomposed into three goals:
0To confirm that each component performs its required function6To confirm that the components are interconnected in the correct manner
To confirm that the components in the product interact correctly and that the product performs its intendedfunction
This approach can be applied to a board constructed from integrated circuits, to a system constructed from printedcircuit boards, or to a complex integrated circuit constructed from a set of simpler functional modules. To simplifythe discussion, this description henceforth will concentrate on the case of an assembled printed circuit boardconstructed from a collection of digital integrated circuits.
At the board level, the second goal [goal b)] maybe achieved using in-circuit test techniques; the first and thirdgoals (goal a) and goal c)) require a functional test. However in-circuit test techniques have significant limitationswhen viewed against evolving surface-mount interconnection technology, for example, the difficulty of makingreliable contact to miniaturized features of the printed circuit board using a bed-of-nails fixture. How, then, mightthese three test goals be achieved if test access becomes limited to the normal circuit connections. plus a relativelysmall number of special-purpose test connections?
Considering goal a), it is clear that the vendor of an integrated circuit used in the board-level design will have anestablished test methodology for that component. The components could be tested on a proprietary ATE system orby using a self-test procedure embedded in the design. Information on the test methodology adopted is typically notavailable to the component purchaser. Even where self-test modes of operation are known to exist, they may not bedocumented and therefore are not available to the component user. Alternative sources of test data for the board testengineer may be the component test libraries supplied with in-circuit test systems or the test programs developed bycomponent users for incoming inspection of delivered devices.
Wherever the test data for a component originates, the next step is to use it once the component has been assembledonto the printed circuit board. If access is limited to the normal connections of the assemibled circuit, this task maybe far from simple. This is particularly true if the surrounding components are complex or if the board designer has
IEEE 1149.1-2013 pdf download
PS:Thank you for your support!
