IEEE 1076-2002 pdf download IEEE Standard VHDL Language Reference Manual
0. Overview of this standard
This clause describes the purpose and organization of this standard, the EEE Standard VHDL LanguageReference Manual.
0.1 Intent and scope of this standard
The intent of this standard is to define VHSIC Hardware Description Language (VHDL) accurately. Itsprimary audiences are the implementor of tools supporting the language and the advanced user of thelanguage. Other users are encouraged to use commercially available books, tutorials, and classes to learn theanguage in some detail prior to reading this standard. These resources generally focus on how to use thelanguage, rather than how a VHDL-compliant tool is required to behave.
At the time of its publication, this document was the authoritative definition of VHDL. From time to time, itmay become necessary to correct and/or clarify portions of this standard. Such corrections and clarificationsmay be published in separate documents. Such documents modify this standard at the time of their publica-tion and remain in effect until superseded by subsequent documents or until the standard is officially revised
0.2 Structure and terminology of this standard
This standard is organized into clauses, each of which focuses on some particular area of the languageWithin each clause,individual constructs or concepts are discussed in each subclause.
Each subclause describing a specific construct begins with an introductory paragraph. Next, the syntax of theconstruct is described using one or more grammatical productions.
A set of paragraphs describing the meaning and restrictions of the construct in narrative form then followUnlike many other IEEE standards, which use the verb shall to indicate mandatory requirements of the stan-dard and may to indicate optional features, the verb is is used uniformly throughout this document. In allcases, is is to be interpreted as having mandatory weight.
Additionally, the word must is used to indicate mandatory weight. This word is preferred over the more com-mon shall, as must denotes a different meaning to different readers of this standard.
To the developer of tools that process VHDL, must denotes a requirement that the standard imposesThe resulting implementation is required to enforce the requirement and to issue an error if therequirement is not met by some VHDL source text.
To the VHDL model developer, must denotes that the characteristics of VHDL are natural conse-quences of the language definition. The model developer is required to adhere to the constraintimplied by the characteristic.
To the VHDL model user, mut denotes that the characteristics of the models are natural consequences of the language definition. The model user can depend on the characteristics of the modelimplied by its VHDL source text.
Finally, each clause may end with examples, notes, and references to other pertinent clauses
IEEE 1076-2002 pdf download
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