ANSI ESDSTM5.3.1-1999 pdf download Machine Model – Component Level
7.3 Test fixture board qualification procedure Use the following procedure for qualification of test fixture boards:
7.3.1 Verify electrical continuity for all pins on the test fixture board.
7.3.2 Capture a waveform for the reference pin pair and any other pin combinations recommended by the manufacturer of each socket on the board using the shorting wire and a ± 400 volt pulse. Verify the waveforms meet the specification in Figure 2.
7.3.3 Capture a waveform on the reference pin pair using the 500 ohm resistor. Use an applied voltage of ± 400 volts. Verify the waveforms meet the specifications in Figure 3.
7.4 Daily tester functionality check procedure Use the following procedure to verify tester functionality:
7.4.1 Test the high voltage discharge path and all associated circuitry at the beginning of each day during which ESD stress testing is performed. Use the tester manufacturer’s recommended procedure. If any failure is detected, do not perform testing with the sockets that use the defective discharge paths. Repair the tester and then requalify it in accordance with section 7.2.
7.4.2 Verify the waveform integrity at least once per shift. If necessary, remove the test fixture board being used and replace with a positive clamp socket test fixture board to facilitate waveform measurements. Verify the waveform using the shorting wire at ± 400 volts, or the stress level to be tested.
8. MM testing requirements Perform ESD stress testing at room temperature in accordance with the procedure below. It is permissible to use any voltage level in Table 3 as the starting stress level. Additional stress levels to those in Table 3 may be used (e.g., the additional voltages in Table 1 ). Three new components may be used at each voltage level and/or pin combination if desired. This will eliminate any possible step stress hardening effects and reduce the possibility of early failure due to cumulative stress on power pins. If three new components are used at each voltage level, it is recommended not to skip any stress level; this will avoid missing possible ESD vulnerability windows. Classify components according to their MM ESD withstand voltage. ESD classification testing shall be considered destructive to the component, even if no component failure occurs.
8.1 Component handling Use ESD damage prevention procedures when handling components before, during and after testing.
8.2 Component static and dynamic tests To determine whether components have failed, perform static and dynamic testing to all data sheet parameters before and after ESD testing. Pin leakage current may only be used as a guide in determining the component ESD withstand voltage. It is not sufficient, especially for complex integrated circuits, to use pin leakage as the only criterion for component failure.
8.3 Test temperature Stabilize the component at room temperature prior to and during the ESD stress testing period.
8.4 Sample Size A minimum of three components is required for each stress level of the test.
8.5 Pin combinations The pin combinations to be used for ESD stressing of all integrated circuit components are given in Table 2. Pin combination (n) is the total number of pin combinations. This varies from component to component depending on the number of power pin groups with the same name.
ANSI ESDSTM5.3.1-1999 pdf download
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