IEEE 1450.6.1-2009 pdf download IEEE Standard for Describing On-Chip Scan Compression
1. Overview
1.1 Scope
This standard defines how the necessary information is passed from scan insertion to pattern generation andfrom pattern generation to dianosis such that different tool vendors could be used for each step independentofon-chip scan compression logic used.
1.2 General
Flows for scan-based test tools are broken into three main stages. Test logic insertion, pattern generation.and diagnosis. Test logic insertion does insertion and verification of test logic, Pattern generation uses thetest logic to make test patterns that can be used to verify if the design is fabricated correctly. Diagnosis isused to identify the failing location in a specific device. Diagnosis information can also be used to increasefuture yield and to solve problems that keep a design from going to market.
This standard, the Open Compression Interface (OCI), defines on-chip scan compression structures(OCSCS), which can be used to pass information from test logic insertion to pattern generation, and frompattern generation to diagnosis, such that interoperability of electronic design automation (EDA) tools ispossible.These structures
Only reveal as much hardware implementation as necessary for pattern generation and diagnosisDo not limit EDA companies from innovating and developing their own compression solutions Support most types of structures for input and output compression
OCSCS are defined here as an extension of IEEE Std 1450.6M-2005 Core Test Language (CTL)].’ Thisstandard highlights the revised CTL syntax and then provides severa examples that cover commoncompression structure types. The actual OCI syntax and semantics appear prior to the examples.
1.3 Conceptual data flow
Figure 1 shows the OCI conceptual data flow from test logic insertion to pattern generation and from patterngeneration to diagnosis. Both the OCI flow (assuming a different vendor for each stage) and the current flowsame vendor for each stage) are shown. Since same-vendor tools have their own way of linking differentstages of the flow together, OCI is only needed for changing stages when any previous step was completedby a different vendor If different vendors were used, then all the data OCI would normally add in theprevious stages is needed
The test logic insertion stage has the best understanding of the test structure being implemented. Test logic insertion tools are developed based on specific compression structures and have many special design rule checks implemented so customers have as good a chance as possible to generate working, highly effective patterns the first time. The time and knowledge necessary to develop all of the design rule checks is significant. Due to this, the OCI flow presumes the pattern generation tool does not need to perform test structure verification. In the case where a design house is integrating a core with in-house design logic, the test structure in the core is presumed to be verified by the core provider and all core-level OCI information needed for pattern generation shall be in the OCI-compliant CTL file the core provider gives the design house. The design house integrating the core is responsible for generating and verifying the final OCI information passed to pattern generation.
IEEE 1450.6.1-2009 pdf download
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