IEEE 62050-2005 pdf download VHDL Register Transfer Level (RTL) synthesis
1.1 Scope
This standard defines a subset of very high-speed integrated circuit hardware description language (VHDL)that ensures portability of VHDL descriptions between register transfer level synthesis tools. Synthesis toolsmay be compliant and yet have fcatures beyond those required by this standard. This standard defines howthe semantics of VHDL shall be used, for example, to model level-sensitive and edge-sensitive logic. It alsodescribes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
Use of this standard should inimize the potential for functional simulation mismatches between modelsbefore they are synthesized and after they are synthesized.
1.2 Compliance to this standard
1.2.1 Model compliance
A VHDL model shall be defined as being compliant to this standard if the modelaUses only constructs described as supported or ignored in this standard
6Adheres to the semantics defined in this standard
1.2.2 Tool compliance
A synthesis tool shall be defined as being compliant to this standard if it
Accepts all models that adhere to the model compliance definition defined in 1.2.1a6Supports language related pragmas defined by this standard
Produces a circuit model that has the same functionality as the input model based on the verificationCprocess as outlined in Clause 5.
1.3 Terminology
The word shall indicates mandatory requirements strictly to be followed in order to conform to the standardand from which no deviation is permitted (shall equals is required to). The word should is used to indicatethat a certain course of action is preferred but not necessarily required; or that (in the negative form) a certain course of action is deprecated but not prohibited (should equals is recommended that). The word mayindicates a course of action permissible within the limits of the standard (may equals is permitted).
A synthesis tool is said to accept a VHDL construct if it allows that construct to be legal input;: it is said tointerpret the construct (or to provide an interpretation of the construct) by producing something that represents the construct A synthesis tool is not required to provide an interpretation for every construct that itaccepts, but only for those for which an interpretation is specified by this standard.
The constructs in the standard shall be categorized as follows:
Supported: RTL synthesis shall interpret a construct, that is, map the construct to an equivalent
hardware representation.
gnored: RTL synthesis shall ignore the construct and produce a warning. Encountering the construct shall not cause synthesis to fail, but synthesis results may not match simulation results. Themechanism, if any, by which RTL synthesis notifies (warns) the user of such constructs is notdefined by this standard. lgnored constructs may include unsupported constructs.
Not Supported: RTL synthesis does not support the construct. RTL synthesis does not expect toencounter the construct, and the failure mode shall be undefined. RTL synthesis may fail uponencountering such a construct. Failure is not mandatory; more specifically, RTL synthesis is allowedto treat such a construct as ienored.
NOTE–A synthesis tool may interpret constructs that are identified as not supported in this standard. However a modethat contains such unsupported constructs is not compliant with this standard.
IEEE 62050-2005 pdf download
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