IEEE 1076.3-1997 pdf download IEEE Standard VHDL Synthesis Packages
1. Overview
1.1 Scope
This standard defines standard practices for synthesizing binary digital electronic circuits from VHDLsource code. It includes the following:
aThe hardware interpretation of values belonging to the BIT and BOOLEAN types defined by lEEEStd 1076-1993’and to the STD_ULOGIC type defined by IEEE Std 1164-1993.
6)A function (STD MATCH) that provides “don’t care” or “wild card” testing of values based on theSTD ULOGIC type.
c)Standard functions for representing sensitivity to the edge of a signal.
dTwo packages that define vector types for representing signed and unsigned arithmetic values, andthat define arithmetic, shift, and type conversion operations on those types.
This standard is designed for use with IEEE Std 1076-1993. Modifcations that may be made to the packagesfor use with the previous edition, IEEE Std 1076-1987, are described in 7.2
1.2 Terminology
The word shall indicates mandatory requirements strictly to be followed in order to conform to the standardand from which no deviation is permitted (shall equals is required to). The word should is used to indicatethat a certain course of action is preferred but not necessarily required; or that (in the negative form) a certaincourse of action is deprecated but not prohibited (should equals is recommended that). The word may indicates a course of action permissible within the limits of the standard (may equals is permitted).
A synthesis tool is said to accept a VHDL construct if it allows that construct to be legal input: it is said tointerpret the construct (or to provide an interpretation of the construct) by producing something that represents the construct. A synthesis tool is not required to provide an interpretation for every construct that itaccepts, but only for those for which an interpretation is specified by this standard.
1.3 Conventions
This standard uses the following conventions:
The body of the text of this standard uses boldface to denote VHDL reserved words (such asadownto) and upper case to denote all other VHDL identifiers (such as REVERSE RANGE orFO0).
The text of the VHDL packages defined by this standard, as well as the text of VHDL examples andcode fragments, is represented in a fixed-width font. All such text represents VHDL reserved wordsas lower case text and all other VHDL identifiers as upper case text.
c)In the body of the text, italics denote words or phrases that are being defined by the paragraph inwhich they occur.
d) VHDL code fragments not supported by this standard are denoted by an italic fixed-width font.
2.References
This standard shall be used in conjunction with the following publications.When the following standards aresuperseded by an approved revision, the revision shall apply.IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual (ANSI).2IEEE Std 1164-1993,IEEE Standard Multivalue Logic System for VHDL Model Interoperability(Std_logic_1164)(ANSI).
3. Definitions
Terms used in this standard. but not defined in this clause. are assumed to be from IEEE Std 1076-1993 andEEE Std 1164-1993.
3.1 argument: An expression occurring as the actual value in a function call or procedure cal.
3.2 arithmetic operation: An operation for which the VHDL operator is +, -, *,/, mod, rem, abs, or **.
3.3 assignment reference: The occurrence of a literal or other expression as the waveform element of a signal assignment statement or as the right-hand side expression of a variable assignment statement.
3.4 don’t care value: The enumeration literal -‘ of the type STD_ULOGIC defined by EEE Std 1164.
1993.
3.5 equality relation: A VHDL relational expression in which the relational operator is =.
3.6 high-impedance value: The enumeration literal Z’ of the type STD ULOGIC defined by IEEE Std1164-1993.
3.7 inequality relation: A VHDL relational expression in which the relational operator is /=.
IEEE 1076.3-1997 pdf download
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