IEEE 1149 4-1999 pdf download IEEE Standard for a Mixed-Signal Test Bus
The standard does not mandate implementation details of the test circuitry, although examples of conformantimplementations are given for illustration.
1.3.2 Interconnect testing
EEE Std 1149.1-1990 provides an effective mechanism for interconnect testing of a PCA populated withdigital components. The first objective of lEEE Std 1149.4-1999 is to provide a similar capability for anassembly such as the one illustrated in Figure 1, populated with analog, digital, and mixed-signal components and discrete components
In seeking to satisfy this objective, one of the fundamental requirements is to provide the ability to detectopen circuits in the interconnections between integrated circuits and to detect and diagnose bridging faultsanywhere in the interconnect regardless of whether they normally carry digital or analog signals. The aim isalso to provide a structure that allows testing in full compatibility with IEEE Std 1149.1-1990 to permitmixed-signal interconnect testing to take place at the same time and using the same procedures as digitainterconnect testing
The range of problems is illustrated in Figure 2, which shows a group of interconnected componentsmounted on a board or other substrate, analog and digital pins being represented by “Aand “D” respectively. The left side of Figure 2 shows open circuits in analog and digital lines and also in an analog interconnection network. The right side of Figure 2 shows a number of short circuits: it should particularly benoticed that short circuits can occur between analog and analog, digital and digital, and analog and digitaines, as well as across discrete components in interconnection networks.
1.3.3 Parametric test The second objective of this standard, parametric test, recognizes the fact that groups of one or more discrete components are often interposed between integrated circuits, performing functions such as level shifting, passive ltering, and ac coupling. The inclusion of discrete components in the interconnection pathway gives rise to the concept of “extended” (as opposed to “simple”) interconnect, as illustrated in Figure 3: to provide for the testing of components in an extended interconnect, the standard denes a framework that will support analog measurements, allowing, for example, impedances of discrete components to be computed. Meeting this objective also allows testing of components such as pull-ups and lter capacitors associated with either analog or digital components.
Also illustrated in Figure 3 is an example of differential interconnect, which is a pair of pathways carrying signals whose information content is dened by the pair of signals rather than by either one signal individually. In the case of digital differential interconnect, these pathways would normally be excited by a single signal, and the activity would be converted back to a single signal after reception. Analog differential interconnect could follow the same pattern, but conversion from or to a single-ended form might take place within the core, or it might not take place at all. Differential interconnect can be treated either as two separate simple interconnects, testing the structural connection between pins, or as a single extended interconnect, testing the functional connection between single-ended transmission point and single-ended reception point.

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