IEC PAS 62162:2000 pdf download Field-induced charged-device model test method for electrostatic discharge withstand thresholds of microelectronic components
2.SCOPE
All packaged semiconductor components, thin film circuits, surface acoustic wave (SAW) components.opto-electronic components, hybrid integrated circuits (HICS), and multi-chip modules (MCMs)containing any of these components are to be evaluated according to this standard. The test methodsdescribed in this standard may also be used to evaluate components that are shipped as wafers or barechips. To perform the tests, the components must be assembled into a package similar to that expectedin the final application. The package used shall be recorded
3.REFERENCE DOCUMENT
EDEC Standard No. 42,“Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS)Devices.
4.TERMS AND DEFINITIONS
Charged device model (CDM) – A specified circuit characterizing an ESD that occurs where a deviceacquires charge through some tribe-electric (frictional) processes and then abruptly touches a groundedobject or surface.
Electrostatic discharge (ESD) – A transfer of electrostatic charge between bodies at differentelectrostatic potentials caused by direct contact or induced by an electrostatic field.Field-induced charging – A charging method using electrostatic induction.
5.CIRCUIT SCHEMATIC FOR THE CDM SIMULATOR5.1 The waveforms produced by the simulator shall meet the specifications of 6.1 through 9.5.2 A schematic for the CDM test circuit is shown in figure 1. (Other equivalent circuits are allowed ifthe generated waveform meets the requirements of 6.1 through 9,) A detachable discharge head (seefigure 1), consisting of the pogo probe, radial resistor, top ground plane, semi-rigid coaxial cable, andthe support arm, is used to initiate the discharge. The discharge path includes a 1 resistive currentprobe of at least 4 GHz bandwidth for waveform monitoring. The cable from the 1 2 resistor to theoscilloscope should also have a bandwidth of at least 3 GHz.
5.3 The Field-Induced Method shall be used to raise the component potential for a subsequent CDMdischarge. The component potential is raised by applying the test voltage to the field charging electrodeshown in figure 1. The size of the charging electrode shall be larger than the size of the component andthe waveform generated shall meet the requirements in table 3.
6. SIMULATOR WAVEFORM VERIFICATION
6.1 The three levels of CDM simulator verification tests are:
G Manufacturer Qualification
. User Verification
G Routine Verification
The tests are described in table 1:
6.2 Manufacturer Qualification – must be done by the manufacturer when the simulator is installed. High-speed instrumentation must be used, including an oscilloscope with a 1 GHz single-shot bandwidth. All three qualification tests of section 9 are required, and the test waveforms must be permanently recorded with copies supplied to the user when requested.
IEC PAS 62162:2000 pdf download
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